The disclosure relates to apparatus and methods of using failure detection and correction (“FDC”) data for yield, quality, and efficiency optimization in back-end assembly processes of semiconductor fabrication, and more specifically in the wire-bonding process in semiconductor fabrication. FIG. 1 illustrates a process for testing wire bonding according to the prior art, which includes after performing maintenance on the wire bonder (operation 102), testing the wire bonding on the IC chip (operation 104) using destructive testing and failure analysis (operation 106). The effectiveness of the result is then evaluated (operation 108) and if the test fails, the process repeats at operation 102. If the testing passes, the integrated circuit (“IC”) chip can be released for production (operation 110).
An emerging challenge in the semiconductor packaging, assembly and testing is the pre-shipment quality and reliability control of various semiconductor parts. This is even more prevalent in the automotive industry. Many automotive manufacturers report semiconductor components as an ever-growing source of recalled parts. That is why many semiconductor module manufacturers and automotive manufacturers now demand an early phase failure detection of semiconductor components. However, the biggest challenge for the semiconductor manufacturers is early failure issues of the ICs due to poor wire bonding, soft shorts, etc.
Conventional methods of quality control for ICs include burn-in processes, in which, the ICs are packaged and then are put in a thermal chamber for several hours and further retested. These conventional processes however are not suitable for testing a high volume of ICs. As is appreciated by skilled persons in the art, a burn-in process is designed to stress the ICs in such a way that any bad ICs (or marginally bad) will usually fail under the testing. The ICs that pass the thermal test(s) are separated from the failed ICs. Only those ICs that pass the thermal test are shipped.
When the volume of the ICs is too high, minor failures may not be detected in the thermal test. Additionally, stringent burn-in processes are very costly. Detection and further classification of failed parts is also difficult to implement. The existing classification processes utilize data collection methods prone to noise, missed triggers, or any other uncontrollable parameter. As such conventional techniques are not very reliable. Therefore it becomes necessary to implement reliable analytical processes of classification.
Some IC fabrication facilities may further implement Advanced Process Control (“APC”) for enhancing throughput, quality and stability at the same time. Some such APC methods include Pad Crack Detection for aluminum wire bonding. Further, while some IC fabrication facilities implement Advanced Process Control (APC) for enhancing throughput, quality and stability at the same time, these solutions are not suitable for calculating failure indicators or using machine learning to segregate normal and abnormal ICs in real time (on-the-fly) or in an offline manner. Nor do prior art solutions use FDC data for throughput improvement or burn-in reduction. Therefore, it would be beneficial to have a tool and a process to test the quality of the wire bonds and further to distinguish between normal and abnormal ICs based on the test results. It would also be advantageous to have a system to classify the abnormal ICs based on the failure indicators.